Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a delay locked loop (DLL) circuit and a duty cycle correction (DCC) circuit of a semiconductor device.
A synchronous semiconductor memory device such as a double data rate synchronous DRAM (DDR SDRAM) is designed to transfer data to external devices in synchronization with an external clock signal inputted from an external device such as a memory controller.
In order to stably transfer data between the memory device and external devices, e.g., the memory controller, it is desirable that the data are outputted from the memory device in synchronization with the external clock applied from the external device to the memory device.
The memory device generates and uses the internal clock signal synchronized with the external clock signal for the stable data transfer. However, the internal clock signal may be out of synchronization with the external clock signal when it is transferred to an output circuit of the data, because it is delayed while passing through internal components of the memory device.
Therefore, in order to stably transfer the data outputted from the memory device, the internal clock signal which is delayed while passing through the internal components of the memory device should be synchronized with the external clock signal by inversely compensating the time at which the data is loaded on the bus, in order to accurately match with the edge or center of the external clock signal applied from the external device.
Examples of such a clock synchronization circuit include a phase locked loop (PLL) circuit and a delay locked loop (DLL) circuit. When frequencies of the external clock signal and the internal clock signal are different from each other, a PLL circuit is used because a frequency multiplication function is needed. On the other hand, when frequencies of the external clock signal and the internal clock signal are equal to each other, a DLL circuit is used because it is less influenced by noise and can be implemented in a relatively small area, as compared to the PLL circuit. For example, in the case of the synchronous semiconductor memory device such as a DDR SDRAM, the frequencies of the external clock signal and the internal clock signal are equal to each other, and thus, the DLL circuit is used as the clock synchronization circuit.
Meanwhile, a synchronous semiconductor memory device such as a DDR SDRAM performs a data input/output operation at rising and falling edges of an internal clock signal. In this case, a duty cycle of the internal clock signal is an important factor which can maximally maintain a timing margin of a high-performance memory system.
That is, when the duty cycle of the internal clock signal does not maintain 50%, an error corresponding to an offset out of 50% reduces the timing margin of the high-performance memory system. Therefore, there is a need for an apparatus for compensating for distortion of the duty cycle which is caused by process, voltage, and temperature (PVT) variations. A duty cycle correction (DCC) circuit used in a DLL circuit is a circuit which corrects the duty cycle of the internal clock signal.
FIG. 1 is a block diagram illustrating a DLL circuit and a DCC circuit of a conventional semiconductor device.
Referring to FIG. 1, the DLL circuit of the conventional semiconductor device includes a first clock phase comparison unit (1st PD) 10, a second clock phase comparison unit (2nd PD) 20, a first delay control unit 30, a second delay control unit 40, a first variable delay line 50, a second variable delay line 60, a first delay model unit (1st REPLICA) 70, and a second delay model unit (2nd REPLICA) 80. Specifically, the first clock phase comparison unit 10 is configured to compare a phase of a source clock REFCLK with a phase of a first feedback clock FBCLK1 and generate a first phase comparison signal PD_OUT1. The second clock phase comparison unit 20 is configured to compare the phase of the source clock REFCLK with a phase of a second feedback clock FBCLK2 and generate a second phase comparison signal PD_OUT2. The first delay control unit 30 is configured to generate a first delay control signal DLY_CONT1 whose value is varied in response to the first phase comparison signal PD_OUT1. The second delay control unit 40 is configured to generate a second delay control signal DLY_CONT2 whose value is varied in response to the second phase comparison signal PD_OUT2. The first variable delay line 50 is configured to output a first DLL clock DLLCLK1 by reflecting a delay amount, which corresponds to the first delay control signal DLY_CONT1, in the source clock REFCLK. The second variable delay line 60 is configured to output a second DLL clock DLLCLK2 by reflecting a delay amount, which corresponds to the is second delay control signal DLY_CONT2, in a clock generated by inverting the phase of the source clock REFCLK. The first delay model unit 70 is configured to generate the first feedback clock FBCLK1 to reflect an actual delay condition of the source clock REFCLK path in the first DLL clock DLLCLK1. The second delay model unit 70 is configured to generate the second feedback clock FBCLK2 to reflect the actual delay condition of the source clock REFCLK path in the second DLL clock DLLCLK2.
Also, referring to FIG. 1, the DCC circuit of the conventional semiconductor device includes a phase mixer 90 configured to mix phases of the first and second DLL clocks DLLCLK1 and DLLCLK2 outputted from the DLL circuit, and output a duty-corrected DLL clock DCC_DLLCLK.
FIG. 2 is a diagram illustrating the operations of the DLL circuit and the DCC circuit of the conventional semiconductor device shown in FIG. 1.
Specifically, FIG. 2 is a waveform diagram of input/output signals when the operations of the DLL circuit and the DCC circuit of the conventional semiconductor device of FIG. 1 are completed.
Referring to FIG. 2, the rising edges of the first feedback clock FBCLK1, the second feedback clock FBCLK2, the first DLL clock DLLCLK1, the second DLL clock DLLCLK2, and the duty-corrected DLL clock DCC_DLLCLK are synchronized with the rising edge of the source clock REFCLK.
At this time, the activation and deactivation durations of the first feedback clock FBCLK1 and the first DLL clock DLLCLK1 are opposite to those of the second feedback clock FBCLK2 and the second DLL clock DLLCLK2. This phenomenon occurs while the phases of the clocks are changed through the operation of the DLL circuit.
Furthermore, the duty-corrected DLL clock DCC_DLLCLK having the duty cycle ratio of 50% can be obtained by mixing the phases of the first DLL clock DLLCLK1 and the second DLL clock DLLCLK2 which are opposite in the activation and deactivation duration length.
As such, in the conventional semiconductor device, the activation and deactivation durations of the first DLL clock DLLCLK1 and the second DLL clock DLLCLK2 are set to be opposite to each other through the operation of the DLLL circuit, and the phases of the first DLL clock DLLCLK1 and the second DLL clock DLLCLK2 are mixed to thereby generate the duty-corrected DLL clock DCC_DLLCLK having the duty cycle ratio of 50%.
However, in order to perform the above-described operation, as illustrated in FIG. 1, the conventional semiconductor device must be designed to include a clock path for a clock corresponding to the rising edge of the source clock REFCLK and a separate clock path for a clock corresponding to the falling edge of the source clock REFCLK.
Since the DLL circuit and the DCC circuit having the configuration of FIG. 1 have two clock paths, more power is dissipated as the frequency of the inputted source clock REFCLK becomes higher and switching increases.
Moreover, a large circuit area is required because two separate sets of components performing similar operations are provided for each unit in order to maintain the two clock paths.